X-Authentication-Warning: delorie.com: mail set sender to geda-help-bounces using -f X-Recipient: geda-help AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:subject:message-id:in-reply-to:references:reply-to :organization:disposition-notification-to:return-receipt-to :mime-version:content-transfer-encoding; bh=osEfVouZPS90qdr7TBgS6kFd0yUf5C9igUpX6OxM5fs=; b=W4UlDA3reQQhBo6QyDGXI8lE/oEIihg1Thiw2EW/cQbmW3aXgxoqMpNH/48xg3lasI /Om26SLWTY+yZTzoGpbJT0VnFXZaOwnRMJ40VA42pPv6q60Kgfth77ZHyZxJ1F2MmkXd c4OCWotK+1kf6YIUzpjehwXNlbytW96Fe+DWiZE3ewjUdoto6DP1driK6Qj5arhg633F H0bgCIlP1vMB1tzHxdxh5e+TA0lXn/Xeq42LQkNrV5UFXCtm+antjm0m30Rqapv8ClSG MKwROlJaHkB7igU7gJb5lAb8+YuErmJwHqYkbEBE2C7F/NvvVpg3Au9FSF214t+Ythqc ps4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:in-reply-to :references:reply-to:organization:disposition-notification-to :return-receipt-to:mime-version:content-transfer-encoding; bh=osEfVouZPS90qdr7TBgS6kFd0yUf5C9igUpX6OxM5fs=; b=j0bb4qzr9JGu89dSi6QGgjcwM3EABoXb+FtwwlyL2kfSANma92le2KQxnRvx5vUdFW ZjM+8V2G6OaDD+kYyYnErJgd3hw+mWPbXCEsRCb8fpmN5W9D6bl0ynNl1egfBj7XfO1G fFNnQ8zMC676Vx6QzBpL71LmVelkLyowmJo3L+MGtrX9+yFw+KMuqcSOosXblJeOP/K5 CWOIVftZzh3ZAV4SnraQiTFBGcyFfMmQvRZPI1RdSs1torW1rt+UzUROP2xhcCjwUdCP CAA642c6/dtApd7/jpRUnh8SxyjvGtu57MxA98Y/KneHvSP4aaKdmz9EEUAlWSBaI1nk Qb/A== X-Gm-Message-State: APjAAAWSzznkz/4lCP+QFVNilgOECemT9oHg5Uv6xfrEtek7KQgVcx3X AW4rkXyuf6FBgFrXGppN4cZF+oU= X-Google-Smtp-Source: APXvYqzKfqSGfxt6SztRBDhNVV4JQ49ZxFsv0LcLuxHAARWOnnvtkaq/SxJ14bkkluIBgFJQ3jsXfQ== X-Received: by 2002:a37:c40d:: with SMTP id d13mr5068197qki.371.1571776171819; Tue, 22 Oct 2019 13:29:31 -0700 (PDT) Date: Tue, 22 Oct 2019 20:29:10 +0000 From: "John L. Males (jlmales AT gmail DOT com) [via geda-help AT delorie DOT com]" To: geda-help AT delorie DOT com Subject: Re: [geda-help] Question: New User - How To Create Very Simple Unique PCB With No Components Message-Id: <20191022202910.7a72089873edeea3807e1d93@gmail.com> In-Reply-To: <20191022170155.29708.qmail@stuge.se> References: <20191019020002 DOT 088a8f4fa249e251d11adfe5 AT gmail DOT com> <20191020183718 DOT e6fccd7def16f88626a4fa24 AT gmail DOT com> <20191021024423 DOT 8d189fc5ca003a8a11384366 AT gmail DOT com> <20191021213833 DOT 6bef6a8bfbaf6d69e36c2527 AT gmail DOT com> <20191022024127 DOT bb67cfef6635bc82b8c747a4 AT gmail DOT com> <20191022170155 DOT 29708 DOT qmail AT stuge DOT se> Organization: Toronto, Ontario X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd11.2) Disposition-Notification-To: jlmales AT gmail DOT com X-Compose-Start-Epoch: `date +%s` Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: geda-help AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-help AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello Peter, Thank you for your reply and information. I have follow up questions and/or comments and related points: The Pin statement in the 3x6 hole part I created as one example was: Pin(300 350 125 90 "101" 0x01) Your great example to make it a pure hole with no connection attribute was: Pin[0 0 3.6mm 0.4mm 3.4mm 3.2mm "" "1" "hole"] If there a difference in context or meaning of the Pin statement when using round brackets vs square brackets? There is a difference in the number of items I used from the connector part I used as basis of my pin statement. Is this related to the type of brackets used as asked just above? Am I correct to assume the first two zeros you used are still for the pin location? If one does not use the "mm" units suffix in your example will that mean the default units is mils? Can one explicitly state mils a a unit of measure? One aspect I learned was the use of 0x101 in the format of the Pin statement created a square hole and graphic inside that collectively indicate pin 1 of the connector. Is this the same parameter in the round brackets syntax I deduced from a connector part that can indicate hole? The second and third value in the round bracket Pin syntax I deduced from the connector part were outside and inside diameter. The first 4 values of the round bracket Pin syntax I used are in mils as I discovered. I am assuming the 5th value in the round bracket values I used is some sort of comment or reference point that I do not see in the PCB nor gerbers I created as test. To clarify the need for a third layer to allow the signal traces from each of the copper sides is not longer a requirement for various reasons. I was aware of 1, 2, 4 layer boards and if I was to use a third layer it would of been for this purpose. Board thickness as you know will affect the capacitance between the upper and lower layer as well as the dielectric of the material between the copper sides. The current indications I have states the boards have a capacitance between 27pF to 39pF. To my way of thinking for the application at hand and related circuits that is a bit wide not just in absolute terms, but on tolerance basis. I believe the wide tolerance is due to using FR4 boards. I think it was Chad that mentioned Polyimide board that my sense was would have smaller capacitance tolerances including from temperature delta point of view. A tighter absolute capacitance tolerance as well as less variation due to temperature delta change are very much both desirable compared to what has been suggested is wider on both points for FR4. Thickness is also a factor because the gap this sensor board sits between is about 0.125". So a board that is also dimensionally stable is important as well. The fixtures the board is attached to are of a warp less design. I will keep in mind and will research different types of board materials for dimension stability and reduce dielectric constants variation. The board does not move, but maybe the metal it is mounted to might pinch the solder mask that would cause unwanted low voltage short that wold render the sensor board useless as well as the application. I had been considering before your comment about the solder mask if running a trace or making a small gap about a via at edge of the copper planes to transition the lower connection to upper side of board that is not in contact with metal fixture to then run the trace top side to the solder pad. This dovetails with your comment about allowing at least 0.5mm space of copper from edge of board. Is it possible to make a copper area a part? If so like the vent holes part I can make the copper area such that there is at least a 0.5mm space from the edge of the board. Why is it important to provide at least a 0.5mm space of copper from side of the board? I ask to learn, not question the suggestion or best practices aspect of the point. the ask if can make the copper area a part assumes the vent holes part will do as I see so far. If not could one edit the text file of the board with the copper sides on it manually to effect the at least 0.5mm clearance of copper from the edge of the board. Do this via the GUI is challenge as one would have to zoom the board so much it may make trying to effect the clearance from the edge challenging or not practical from a GUI point of view. I like your suggestion of using oshpark.com to test things like fit to the mounting fixture the board will be. I could test the capacitance as well of the board from oshpark.com and it would allow me to compare the oshpark.com board to high end boards for capacitance, capacitance variation due to dielectric, and variation due to temperature delta change. I have skipped questions I have of the "Element" statement and "ElementLine" for now until I have the "Pin" statement questions I asked above sorted out that I understand for my needs. John L. Males Toronto, Ontario Canada 22 October 2019 16:29 -0400 EDT ================================================================ 2019-10-22 19:30:27+0000-UTC Time: 1571772627 PC/System time 22 Oct 19:30:27 ntpdate[50905]: ntpdate 4.2.8p12-a (1) 22 Oct 19:30:42 ntpdate[52514]: step time server 206.108.0.132 offset 0.008908 sec FreeBSD 11.3-STABLE FreeBSD 11.3-STABLE #0 r349903: Thu Jul 11 16:13:47 UTC 2019 root AT releng2 DOT nyi DOT freebsd DOT org:/usr/obj/usr/src/sys/GENERIC (Work in progress alternative to Linux Kernel of its own right, Debian, and other Linux based Kernel distributions determined.) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) Intel(R) Core(TM) i3-2367M CPU @ 1.40GHz (1396.86-MHz K8-class CPU) dev.cpu.0.temperature: 67.0C dev.cpu.1.temperature: 68.0C dev.cpu.2.temperature: 63.0C dev.cpu.3.temperature: 63.0C hw.acpi.thermal.tz0.temperature: 75.1C vmstat -s: 67397552 cpu context switches 1336007 device interrupts 307073 software interrupts 12626753 traps 247567285 system calls 27 kernel threads created 2759 fork() calls 521 vfork() calls 0 rfork() calls 0 swap pager pageins 0 swap pager pages paged in 0 swap pager pageouts 0 swap pager pages paged out 6660 vnode pager pageins 82253 vnode pager pages paged in 189 vnode pager pageouts 3143 vnode pager pages paged out 0 page daemon wakeups 6065840 pages examined by the page daemon 0 clean page reclamation shortfalls 0 pages reactivated by the page daemon 143753 copy-on-write faults 730 copy-on-write optimized faults 9183392 zero fill pages zeroed 0 zero fill pages prezeroed 35 intransit blocking page faults 12678412 total VM faults taken 9235 page faults requiring I/O 0 pages affected by kernel thread creation 130627 pages affected by fork() 18364 pages affected by vfork() 0 pages affected by rfork() 11879687 pages freed 0 pages freed by daemon 3100745 pages freed by exiting processes 269736 pages active 553198 pages inactive 23882 pages in the laundry queue 201072 pages wired down 959843 pages free 4096 bytes per page 2212682 total name lookups cache hits (92% pos + 3% neg) system 0% per-directory deletions 0%, falsehits 0%, toolong 0% Boot time : 1571762712 procs memory page disks faults cpu0 cpu1 cpu2 cpu3 r b w avm fre flt re pi po fr sr ad0 pa0 in sy cs us sy id us sy id us sy id us sy id 0 0 0 27854872 3839304 1277 0 1 0 1196 611 0 0 135 24929 6787 15 6 80 15 5 80 15 5 80 15 5 80 memory info: real memory = 8589934592 (8192 MB) avail memory = 8166465536 (7788 MB) last pid: 57742; load averages: 0.45, 0.45, 0.54 up 0+02:45:31 19:30:43 57 processes: 2 running, 55 sleeping Mem: 1054M Active, 2161M Inact, 93M Laundry, 786M Wired, 316M Buf, 3748M Free Swap: 48G Total, 48G Free hw.physmem: 8463925248 hw.usermem: 7640150016 hw.realmem: 8589934592 total used free shared buffers cached Mem: 8030732 1978872 6051860 0 0 0 Swap: 50331644 0 50331644 swapinfo: Device 1K-blocks Used Avail Capacity /dev/ada0s1b 50331644 0 50331644 0% vmstat: procs memory page disks faults cpu r b w avm fre flt re pi po fr sr ad0 pa0 in sy cs us sy id 0 0 0 27855896 3838880 1277 0 1 0 1197 611 0 0 135 24930 6787 15 5 80 Message replied to: Date: Tue, 22 Oct 2019 17:01:55 +0000 From: "Peter Stuge (peter AT stuge DOT se) [via geda-help AT delorie DOT com]" To: "John L. Males \(jlmales AT gmail DOT com\) \[via geda-help AT delorie DOT com\]" Subject: Re: [geda-help] Question: New User - How To Create Very Simple Unique PCB With No Components > John L. Males (jlmales AT gmail DOT com) [via geda-help AT delorie DOT com] > wrote: > > Is the "Pin" attribute of the part "Element" a Via or just a > > pin with hole for the layer the pin is assigned to? > > A Pin inside an Element is on one hand a connection point for > one part in the netlist (irrelevant for your board) and on > another hand a drilled hole through all layers and a copper > ring on all layers. > > This is far more than you need. By adding the "hole" flag to > the Pin you can indicate that this Pin is actually primarily > a hole. Here's a footprint that I've created for a single M3 > mounting hole: > > Element[0x00000000 "M3 mount" "" "" 0 0 -1mm -1mm 0 100 ""] > ( > Pin[0 0 3.6mm 0.4mm 3.4mm 3.2mm "" "1" "hole"] > ) > > 3.2mm is the drill diameter. What are the 3.6, 0.4 and 3.4 > measurements? > > 3.6mm is Thickness - the outer diameter of the copper ring, > were this Pin not a hole. Being a hole, no copper ring is > generated. > > 0.4mm is Clearance - add this to Thickness above to get the > diameter of the generated copper removal around the center of > the hole. This applies equally to holes (with "hole" flag; no > copper) and pins (without "hole" flag). > > 3.4mm is Mask - diameter of the generated circular opening of > the solder mask around the center of the hole. Applies to > holes and pins. > > > > For example I have created a part that is just the set of > > holes using the "Pin" attribute of the part "Element" so > > the set of 6x3 holes is spaced exactly as needed and with a > > home reference point. > > That's a great solution. > > > Some general points: > > I've not seen any PCB fab offer 3-layer boards. You can get > 1, 2 or 4. You'll do fine with 2. > > Please mind that PCB thickness is very much inexact. > Fiberglass cores (sometimes called prepreg) are built by the > PCB fab stacking multiple 10-100µm layers to roughly the > required height. This is a mechanical process which has > variations - those may be quite significant, depending on > which capacitance tolerance you require. Expect no less than > ±100µm thickness tolerance. > > Please also do research different dielectric materials. FR4 > is the entry level material, quite a loose weave, exhibiting > fairly high variation. Many PCBs with strict signal integrity > requirements can not afford to use FR4, but need a much > tighter weave in the core, to reduce dielectric constant > variation significantly. You may or may not need to consider > this, and may have to work with select, higher-end PCB fabs > who control more precise processes and offer different core > materials, again depending on your tolerance requirement. > > Remember to leave any area of the PCB which rests against > metal (on the back if I understood you correctly) free of > copper, even if you use solder mask. The solder mask is a > think lacquer and will wear off with friction. > > And remember to leave at least 0.5mm to the PCB edge free of > copper. > > > In North America you could start with ordering PCBs from > oshpark.com, they do efficient pooling such that you don't > have to pay much per board. If you have the time this means > you can do a test run or two of just a few boards, on one > hand to practice the process with your software before > contacting a higher-end fab, on another hand to get some > actual boards to test functionally. > > > > Kind regards > > //Peter -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQQxRId2q5JPHFiozTr5X9dS0HpoEAUCXa9mlgAKCRD5X9dS0Hpo EF2zAJ0ZN5rjzdc1eComAiymLAGZ90h51wCfZN7bzaYRnueGWugf2LbIgZ6GxiI= =VyZc -----END PGP SIGNATURE-----