From: "Campbell, Rolf [SKY:1U32:EXCH]" Newsgroups: comp.os.msdos.djgpp Subject: Re: AMD processors and assembly language Date: Tue, 14 Mar 2000 16:03:39 -0500 Organization: Nortel Networks Lines: 20 Message-ID: <38CEA92B.33F326B@americasm01.nt.com> References: <0damcssmqrmoiphi95hu789fkkfhpgk327 AT 4ax DOT com> NNTP-Posting-Host: wmerh0tk.ca.nortel.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.72 [en] (X11; I; HP-UX B.10.20 9000/785) X-Accept-Language: en To: djgpp AT delorie DOT com DJ-Gateway: from newsgroup comp.os.msdos.djgpp Reply-To: djgpp AT delorie DOT com Damian Yerrick wrote: > >Yes, most likely, but what I wanted to point out is the awesome > >overcloackbility of the athlons ... > > Speaking of Athlon: > Athlon is a VLIW RISC chip with a hardware Intel emulator frontend. And, ironically, the 'emulation' runs faster than the original (at the same clock speed). > Crusoe is a VLIW RISC chip with a software Intel emulator frontend > called "Code Morphing(tm)". IA64 Merced Itanium (or whatever it's > called) is a VLIW RISC chip with a totally new instruction set. -- (\/) Rolf Campbell (\/)