Message-ID: <3874F8E1.7F0ADC10@bigfoot.com> From: JP Morris Organization: Aircraft Liberation Front X-Mailer: Mozilla 4.7 [en] (X11; I; Linux 2.3.35 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.os.msdos.djgpp Subject: Re: assembly language and AMD processors References: <01JKDMTWXER68WWRAH AT SLU DOT EDU> <852ldj$jnj$1 AT nets3 DOT rz DOT RWTH-Aachen DOT DE> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 Date: Thu, 06 Jan 2000 20:19:45 +0000 NNTP-Posting-Host: 212.56.119.112 X-Complaints-To: abuse AT plus DOT net DOT uk X-Trace: wards 947190092 212.56.119.112 (Thu, 06 Jan 2000 20:21:32 GMT) NNTP-Posting-Date: Thu, 06 Jan 2000 20:21:32 GMT To: djgpp AT delorie DOT com DJ-Gateway: from newsgroup comp.os.msdos.djgpp Reply-To: djgpp AT delorie DOT com Hans-Bernhard Broeker wrote: > > GAMMELJL AT slu DOT edu wrote: > > Is the assembly language instruction set for an AMD processor > > identical to the instruction set for the Intel 486 architecture? > > Or is it more like the instruction set for an alpha processor? > > No. The AMD 'Athlon' has the usual x86 instruction set, plus some > extensions found in older AMD processors like K6-II and K6-III > (3DNow!, replacing Intel's ISSE stuff). If that weren't the case, > nobody would be using that new processor for Windows machines, > would they? IIRC, the AMD chips have a RISC core that emulates the CISC architecture. There were rumours of a way to get the CPU to execute it's native RISC instructions (which would be pretty smart), but rumours are all I've heard. > > -- > Hans-Bernhard Broeker (broeker AT physik DOT rwth-aachen DOT de) > Even if all the snow were burnt, ashes would remain. -- JP Morris - aka DOUG the Eagle (Dragon) -=UDIC=- DOUG-15 AT bigfoot DOT com Fun things to do with the Ultima games (http://ithe.cjb.net) Developing a U6/U7 clone (http://fly.to/ire) d+++ e+ N+ T++ Om U123456!7'!8!KA u++ uC+++ uF+++ uG---- uLB---- uA--- nC+ nR---- nH+++ nP++ nI nPT nS nT wM- wC- y a(YEAR - 1976)