Date: Wed, 3 Mar 1999 11:29:23 -0500 Message-Id: <199903031629.LAA28097@envy.delorie.com> X-Authentication-Warning: envy.delorie.com: dj set sender to dj AT envy DOT delorie DOT com using -f From: DJ Delorie To: djgpp AT delorie DOT com In-reply-to: (message from Baraz Akos 950918 on Wed, 3 Mar 1999 17:15:33 +0100) Subject: Re: a make problem References: Reply-To: djgpp AT delorie DOT com Gnu make with gcc has a way of managing dependencies for include files automatically. See http://www.delorie.com/gnu/docs/make/make_43.html or look for "Generating Dependencies Automatically" in "info make". I think that would be a better solution than what you're attempting to do below, which usually results in a list of explicit rules instead of a handful of implicit rules. Note that you can mix explicit rules with implicit ones, and make will accumulate dependencies: %.o : %.cpp gcc -c $*.cpp one1.o : $(ONE_DEP) one2.o : $(ONE_DEP) two1.o : $(TWO_DEP) two2.o : $(TWO_DEP) two3.o : $(TWO_DEP) > I've got a problem with makefile making. > I'd like to compile a lot of target with different dependecies. > > Got variables like this: > > ONE_C = one1.cpp one2.cpp > ONE_DEP = x.h y.h > > TWO_C = two1.cpp two2.cpp > TWO_DEP = z.h x.h w.h > > and I want to compile them by ONE rule, but $(%) doesn't work in place of > the deps.