From: moorer AT cs DOT man DOT ac DOT uk (Richard Moore)
Newsgroups: comp.os.msdos.djgpp
Subject: Re: Make files
Date: 23 Sep 1996 14:04:38 GMT
Organization: Dept of Computer Science, University of Manchester, U.K.
Lines: 63
Message-ID: <5265dm$pu2@m1.cs.man.ac.uk>
References: <32461180 DOT 29C6 AT stud DOT tue DOT nl>
NNTP-Posting-Host: n7d.cs.man.ac.uk
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To: djgpp AT delorie DOT com
DJ-Gateway: from newsgroup comp.os.msdos.djgpp

Richard L.F. van Paasen (R DOT L DOT F DOT v DOT Paasen AT stud DOT tue DOT nl) wrote:
: Hi, (subject: write a generic makefile)

: But man, this seems not straightforward for a non-unix programmer. Is
: here
: someone who has written such a (generic) makefile, and who wants to
: share it
: with me (and all newbies that read this newsgroup) ? I'd be glad to
: hear.

Here is the makefile for a project I was working on a while ago, you
can use it as a template.

Rich.

---CUT-HERE---8<--------


# Note! Dependencies are done automagically by 'make depend', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).

CC	=	gcc
LDLIBS	=	
LDFLAGS	=	

DEBUG	=	-g -Wall
OPTIMIZE =	

CFLAGS	=	$(DEBUG) $(OPTIMIZE) 

# These rules will compile all your c files to object files
.c.s:
	$(CC) $(CFLAGS) -S $<
.c.o:
	$(CC) $(CFLAGS) -c $<

# Add your object filenames here
OBJS=	your-objects-go-here.o

# This is a special rule to link the project 
build: $(OBJS)
	$(CC) $(CFLAGS) $(LDFLAGS) -o output-filename $(OBJS) $(LDLIBS)

depend:
	$(CPP) $(CFLAGS) -MM *.c > _depend

#
# include the dependency file if there is one
#
ifeq (.depend,$(wildcard _depend))
include _depend
endif

---CUT-HERE---8<--------

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