Sender: nate AT cartsys DOT com
Message-ID: <37969AA1.2B135315@cartsys.com>
Date: Wed, 21 Jul 1999 21:14:25 -0700
From: Nate Eldredge <nate AT cartsys DOT com>
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To: djgpp-workers AT delorie DOT com
Subject: Re: .align directives in libc.a
References: <Pine DOT SUN DOT 3 DOT 91 DOT 990721171710 DOT 429J-100000 AT is>
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Reply-To: djgpp-workers AT delorie DOT com

Eli Zaretskii wrote:
> It would be nice if we could finally close this issue
> for good, at least until Intel come out with a chip that fetches on
> 32-byte boundary ;-)

My AMD K6-3 has 32 byte cache lines (and I think the K6-2 did as
well)...

But didn't SET post something to the effect that even with 32-byte cache
lines, 16-byte alignment isn't noticeably worse?

-- 

Nate Eldredge
nate AT cartsys DOT com